`timescale 1ns / 1ps
module DATA_RES #(
    parameter F_FOSR = 1,
    parameter F_FORD = 2
)(
    input wire          clk,
    input wire          rst_n,
    input wire          bit_data,

    output wire[31:0]   r_data,
    input  wire         r_ready,
    output wire         rdata_valid,
    input wire[31:0]    d_offset
);


wire[31:0] t_data;
wire       t_valid;
wire       t_ready;
wire       ts_ready;

assign rdata_valid = t_valid;
assign r_data = t_data;
assign t_ready = r_ready;

wire[31:0]  m_data;
wire        m_valid;
wire        m_ready;

reg[31:0] fdata;
reg       fvalid;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        fdata <= 0;
        fvalid <= 0;
    end else begin
        fvalid <= 1;
        if (bit_data == 1) begin
            fdata <= 32'h0000_00001;
        end else begin
            fdata <= 32'hffff_ffff;
        end
    end
end

wire c1, c2, c4, c5;
wire[31:0] c3, c6;

CIC64 #(
    .FOSR(F_FOSR),
    .FORD(F_FORD)
)   u_CIC64
(
    .clk        (clk        ),
    .rst_n      (rst_n      ),

    .data       (fdata      ),
    .data_valid (fvalid     ),
    
    .tvalid     (t_valid    ),
    .tready     (t_ready    ),
    .tdata      (t_data     ),
    .data_offset(d_offset)
);
    
endmodule